Flash E.sup.2 PROM array with mingle polysilicon layer memory cell
US5359573A · kind A · utility
5Cited by
5References
5Claims
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Inventor
Key dates
| Filing date | Jun 19, 1992 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Jun 19, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In embodiments of flash E.sup.2 PROM arrays, an access transistor is included in each cell thereof, in series with the floating transistor of the cell, the access transistor being used to avoid the problem of drain disturbance in cells other than the cell being programmed. The connection of the control gates in certain of these arrays is such that gate disturbance on the floating gate transistors in those cells not being programmed is reduced or eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.