Timing recovery circuit for synchronous waveform sampling
US5359631A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1992 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Sep 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.