Programmable frequency divider in a phase lock loop
US5359635A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1993 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Apr 19, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. A programmable divider latches a program integer for providing a latch integer, compares the latch integer to a constant integer, and generates a flag signal having a first state when the latch integer mismatches the constant integer and a second state when the latch integer matches the constant integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for providing the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.