Early scalable instruction set machine alu status prediction apparatus
US5359718A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1991 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Mar 29, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4991
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus implementing an algorithm for generating carries due to the second instruction of an interlocked instruction pair when executing all combinations of logical as well as arithmetic instruction pairs is developed. The algorithm is then applied to three interlock collapsing ALU means implementations that have been proposed. The critical path for calculating the carries is first presented. Next the expression for generating these carries is used to derive a fast implementation for generating overflow which is implemented in the apparatus. The resulting ALU status determination apparatus includes a three-to-one ALU means for executing plural instructions which can predict the status of three-to-one ALU operations related to the presence/absence of carries incorporated in the three-to-one ALU designed to execute a second instruction of a pair of instructions in parallel and whether or not the second instruction of the pair is independent or dependent on the result of the operation of the first instruction. Additionally, an implementation scheme for predicting result equal to zero is developed for the three-to-one ALU operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.