Method and apparatus for rapidly switching processes in a computer system
US5361337A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 1992 |
| Grant date | Nov 1, 1994 |
| Priority date | — |
| Expiry date | May 8, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.