Circuit for fast page mode addressing of a RAM with multiplexed row and column address lines
US5361339A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1992 |
| Grant date | Nov 1, 1994 |
| Priority date | — |
| Expiry date | May 4, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for addressing a random access memory (RAM) and for rotating an image by reading it into and then out from a page buffer, where all transfers, whether by column or row, are performed substantially in a fast page mode in which the same row address is maintained from one access to the next. The column address lines of RAM devices are connected to the 5 or 6 least significant bits of the vertical and horizontal address counters of the image, and the row address lines are connected to the remaining most significant bits of the vertical and horizontal counters of the image. Therefore, whether the system is accessing the image data in the vertical or horizontal direction, there will be at least 31 fast page mode accesses for every one slow access, and the average speed of transfers in either direction will approximate the fast page mode speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.