Integrated data processor having mode control register for controlling operation mode of serial communication unit
US5361374A · kind A · utility
10Cited by
16References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1993 |
| Grant date | Nov 1, 1994 |
| Priority date | — |
| Expiry date | Apr 21, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a command of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.