Apparatus and method for emulation routine instruction issue
US5361389A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1993 |
| Grant date | Nov 1, 1994 |
| Priority date | — |
| Expiry date | Sep 27, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for emulation routine instruction issue comprises a bus signal router, a state machine, a virtual program counter (VPC) circuit, an emulated program counter (EPC), a summing circuit, an opcode storage register, and a pointer storage register. The VPC circuit maintains the VPC value under the direction of the state machine. In response to a next instruction request issued by the central processing unit (CPU), the state machine outputs the VPC to an instruction address bus, transferring the host instruction stored at the address indicated by the VPC to the instruction bus for issue to the CPU. After a next host instruction request, the state machine updates the VPC value. Concurrent with the execution of the current emulation routine, the state machine prefetches the nest emulation routine pointer (NERP) by issuing DMA commands and commands to the EPC, the opcode storage means, and the pointer storage means. If the final host instruction in the current emulation routine has been reached, the state machine assigns the NERP to the VPC and outputs the VPC to the instruction address bus. A method for Emulation Routine Instruction Issue comprises the steps of determining if a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.