Method for producing semiconductor memory device having a planar cell structure
US5362662A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1993 |
| Grant date | Nov 8, 1994 |
| Priority date | — |
| Expiry date | May 3, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
A semiconductor memory device includes a substrate, a first diffusion region composed of at least one longitudinal and continuous source region which is disposed on the substrate and commonly used for a plurality of memory transistors, and a second diffusion region composed of at least one longitudinal and continuous drain region which is disposed in parallel with the first diffusion region and commonly used for the plurality of memory transistors. A refractory metal film is disposed on each of the first and second diffusion regions. An electric insulation film is disposed on the refractory metal film. A plurality of parallel gate electrodes are disposed crossing over the first and second diffusion regions. And a gate oxide film is arranged to electrically insulate the gate electrodes from the diffusion regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.