Comparator with controlled hysteresis
US5362994A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1992 |
| Grant date | Nov 8, 1994 |
| Priority date | — |
| Expiry date | Oct 13, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/011
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hysteresis comparator is disclosed which utilizes an on-chip bias generator, and incorporates circuitry which renders the decision voltages V.sub.P and V.sub.N insensitive to semiconductor process variations, independent of any critical reference voltages, and proportional to absolute temperature. Current sources coupled to positive and negative bias voltages are utilized to generate precise voltages across resistors to set the magnitude of V.sub.P and V.sub.N, which magnitudes are set by the ratios of like components existing within the same integrated circuit. Hysteresis comparators with precise and repeatable decision voltages can be implemented while consuming a minimum amount of semiconductor area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.