Offset-insensitive switched-capacitor gain stage
US5363102A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1993 |
| Grant date | Nov 8, 1994 |
| Priority date | — |
| Expiry date | Mar 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/486
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An IC chip formed with an analog-to-digital converter having a switched-capacitor programmable gain stage and employing a switched-capacitor sigma-delta modulator. The chip includes pins to receive a number of different audio input signals which are selectively connectible to buffer amplifiers the outputs of which are directed to a switch to select one output for further processing. The selected buffer amplifier output is d-c coupled to an input signal terminal of a switched-capacitor programmable gain stage. The output of this gain stage is coupled to an output stage including an op-amp and associated switched-capacitor circuitry. The programmable gain stage has a reference input terminal which is connected through an IC chip pin to an external capacitor the other electrode of which is returned to signal common. This capacitor develops a d-c voltage corresponding to the offset voltages of the operative buffer amplifier and the op-amp, and including a component corresponding to charge-injection from MOS switches. Absorption of such d-c voltages by this capacitor prevents those voltages from being significantly gained by the amplifier circuitry, and thereby prevents those voltages f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.