Variable size queue circuit for buffering data transfers from a processor to a memory
US5363486A · kind A · utility
10Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1993 |
| Grant date | Nov 8, 1994 |
| Priority date | — |
| Expiry date | Jul 13, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a memory capable of storing a plurality of data words, and a central processing unit for outputting data words to be stored in the memory. A method and apparatus for facilitating transfer of the data words from the central processing unit to the memory involve accepting and temporarily storing in a storage portion each data word from the central processing unit and then subsequently storing in the memory each temporarily stored data word, the maximum number of data words which can be temporarily stored being selectively set to one of first and second values which are different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.