Apparatus for and method of conditionally aborting an instruction within a pipelined architecture
US5363490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1992 |
| Grant date | Nov 8, 1994 |
| Priority date | — |
| Expiry date | Feb 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for and method of aborting the remainder of a microinstruction if a branch by that microinstruction or a subsequent microinstruction renders the results of said microinstruction to be invalid. Within an instruction processor having the capability for pipelined operation, the sensitivity of an operation of a microinstruction to the branch condition may be indicated by one or more abort bits. If an abort bit is set and the corresponding branch condition occurs, the remainder of the microinstruction is aborted. By thus indicating the sensitivity to a branch, the microinstruction can proceed under full pipeline operation until such time as a branch condition actually occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.