Method of manufacturing an EEPROM having an erasing gate electrode
US5364805A · kind A · utility
13Cited by
7References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1991 |
| Grant date | Nov 15, 1994 |
| Priority date | — |
| Expiry date | Jul 8, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A memory cell array is formed of a plurality of nonvolatile memory cell transistors arranged in a matrix form. The patterns of the control gate electrode and the source region of each memory cell transistor are formed in parallel and the pattern of the erasing gate electrode is formed to intersect the source region and control gate electrode patterns. A field oxide film is formed in an intersecting portion between the source region and the erasing gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.