Dynamic random access memory device
US5365477A · kind A · utility
93Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1992 |
| Grant date | Nov 15, 1994 |
| Priority date | — |
| Expiry date | Jun 16, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/05
Abstract
A vertically integrated DRAM cell having a storage time of at least 4.5 hours at room temperature, formed from a wide-bandgap semiconductor such as GaAs or AlGaAs, in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor, with the middle p-n layers being common to both. Similarly, a p-n-p transistor can be merged with an n-p-n storage capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.