Method of manufacturing semiconductor device employing oxide sidewalls
US5366913A · kind A · utility
9Cited by
4References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1992 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Oct 15, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/111
Abstract
When a semiconductor is manufactured by a resist mask process while using photolithography techniques, the gate wiring width is increased without increasing the cell area by providing a sidewall on the gate mask and using the sidewall as a mask. The sidewall is produced by applying a CVD oxide film to the mask and removing the oxide film by anisotropic etching. This provides a minimum gate line width of 0.7.mu. and a minimum space width of 0.3.mu..
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.