Method and apparatus for performing parallel zero detection in a data processing system
US5367477A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1993 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Nov 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49905
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A zero detection method (FIG. 5) and a zero detection apparatus (FIGS. 2-4) involves determining if the sum of at least two operands and a carry-in bit will produce a zero result. The zero detection is performed in parallel to another system calculation, such as an addition or subtraction of the two operands. The zero detection logic has a hierarchical structure (see FIG. 4) which is used to reduce logic and quicken the zero detect process of FIG. 5. Zero detection may occur for more than one group of bits within the two operands. The zero detection is used, in a preferred form, primarily in floating point operations such as floating point additions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.