Semiconductor memory device capable of correctly and serially reading stored data signals
US5367486A · kind A · utility
34Cited by
10References
10Claims
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Key dates
| Filing date | Sep 26, 1991 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Sep 26, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a serial memory, data signal holding circuits for temporarily holding data read from memory cells are provided as a data register. One holding circuit includes a latch circuit and capacitors connected to input/output nodes of the latch circuit, respectively. The capacitors contribute to stabilizing the latch function by the latch circuit. Therefore, when transistors turn on in response to a serial selection signal at a high level, the latch circuit is prevented from being inverted by the potentials of a serial bus line pair. Accordingly, generation of reading errors is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.