Random access memory having control circuit for maintaining activation of sense amplifier even after non-selection of word line
US5367495A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 28, 1992 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Dec 28, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A MOS memory device operating at high speed which is so constructed as to hold the sense amplifier activating signals SAP and SAN at high potential and at low potential, respectively, even after the completion of a memory access, and keep the sense amplifier 30a in activated state to hold read data from memory cells. This memory device includes a block decoder which designates mutually different cell array blocks synchronized with a row selection signal RAS and a column selection signal CAS so that it is possible at the time of input of the column selection signal CAS to execute write/read operation in page mode that extends over the cell array blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.