Hypercube processor network in which the processor indentification numbers of two processors connected to each other through port number n, vary only in the nth bit
US5367636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1993 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Nov 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17343
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processor network comprised of a plurality of nodes, each node including a processor containing a number of I/O ports, and a local memory. Each processor in the network is assigned a unique processor ID (202) such that the processor IDs of two processors connected to each other through port number n, vary only in the nth bit. Input message decoding means (200) and compare logic and message routing logic (204) create a message path through the processor in response to the decoding of an address message packet and remove the message path in response to the decoding of an end of transmission (EOT) Packet. Each address message packet includes a Forward bit used to send a message to a remote destination either within the network or to a foreign network. Each address packet includes Node Address bits that contain the processor ID of the destination node, it the destination node is in the local network. If the destination node is in a foreign network space, the destination node must be directly connected to a node in the local network space. In this case, the Node Address bits contain the processor ID of the local node connected to the destination node. Path creation means in s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.