Reconfigurable multi-way associative cache memory
US5367653A · kind A · utility
86Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 1991 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Dec 26, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable set associative cache memory can be reconfigured from 2.sup.x way to 2.sup.y way set associative cache memory by effectively merging a predetermined number of least significant bits of the tag field of the main memory address with the line field of the main memory address. The effective merging is provided by logically merging least significant bits of the tag field with a reconfiguration designation. As a result, Y-X+1 different configurations of cache memory can be obtained using the Y-X least significant bits of the tag field merged with the cache memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.