Memory and associated method including an operating mode for simultaneously selecting multiple rows of cells
US5367655A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1991 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | Dec 23, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory (10) that has a shorter access time and higher reliability in a special mode of operation. In one form, the memory (10) has a special mode of operation in which multiple memory rows are simultaneously selected. As a consequence, multiple memory cells (44) are used to drive each bit line pair. Using multiple memory cells (44) to drive each bit line pair allows the bit lines to be driven to the proper logic state in a shorter time. This speeds up accesses to memory (10). Using multiple memory cells (44) to drive each bit line pair also improves the reliability of memory (10). Because multiple memory cells (44) are used to drive the same bit line pair, a failure of one memory cell (44) still leaves one or more functioning memory cells (44) to drive the correct logic state on the bit line pair. The memory may be incorporated in a cache controller of a data processing system in which only a part of the memory is being used. The extra unneeded memory cells may be used to help drive the bit lines to allow the cache controller to execute operations more quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.