Parallel computer system including efficient arrangement for performing communications among processing node to effect an array transposition operation
US5367692A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 1991 |
| Grant date | Nov 22, 1994 |
| Priority date | — |
| Expiry date | May 30, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing element array and a controller. The processing element array comprises a plurality of processing element nodes interconnected by a plurality of communications links in the form of a hypercube. Each processing element node has a memory including a plurality of storage locations for storing data, and in addition has a hypercube address. The controller controls the processing element nodes in parallel to enable the transfer of data items in a selected manner among the storage locations of the processing element nodes in a series of communications steps. The controller generates a base communications table and enables the processing element nodes to, in parallel, generate respective processing element node communications schedule tables as a selected function of the base communications table and the respective node's hypercube address. Each processing element node communications schedule table associates, for each of a plurality of iterations, storage locations of the processing element node's memory with a dimension of the hypercube. The controller then enables the processing element nodes to, in parallel in a series of transfer iterations, facilitate the transfer of data…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.