Sidewall-sealed poly-buffered LOCOS isolation
US5369051A · kind A · utility
30Cited by
9References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 5, 1992 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Aug 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming LOCOS isolation regions which includes the steps of forming a polysilicon buffer layer between the pad oxide layer and the nitride layer and forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation region has reduced oxide encroachment into the active moat region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.