Method for constructing a reduced capacitance chip carrier
US5369059A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1992 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Apr 8, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T156/1002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making an integrated circuit chip carrier having reduced and regulable interlead capacitance and reduced glass chip formation. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.