Level translator capable of high speed operation
US5369318A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1993 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Jun 23, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017518
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The output terminal of an ECL circuit is directly connected to the input terminal of a CMOS output circuit. The CMOS output circuit has a transistor which sets the threshold voltage of the CMOS output circuit nearly midway between ECL logic levels. A first reference voltage generating circuit has substantially the same arrangement as the CMOS output circuit and outputs a potential midway between CMOS logic levels as a first reference voltage Vref1. The first reference voltage Vref1 is made variable. A second reference voltage generating circuit has substantially the same arrangement as the ECL circuit and outputs a potential which is midway between the ECL logic levels as a second reference voltage Vref2. A comparator makes a comparison between the first and second reference voltages Vref1 and Vref2 and controls the first reference voltage generating circuit and the CMOS output circuit so that the first and second reference voltages Vref1 and Vref2 may become equal to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.