Comparator having temperature and process compensated hysteresis characteristic
US5369319A · kind A · utility
32Cited by
20References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1992 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Dec 21, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/02337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A MOS hysteresis comparator having a source transistor bias circuit which generates a source current Is that compensates for temperature and manufacturing process variations, thereby providing a hysteresis characteristic which is substantially insensitive to such temperature and manufacturing process variations. The source transistor bias circuit includes a set of MOS transistors which replicate the comparator load currents which occur at the switch points of the comparator, and a source transistor which mirrors the sum of the replicated currents to form the source current Is of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.