Method for assuring that an erase process for a memory array has been properly completed
US5369616A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1994 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Mar 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0664
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.