Semiconductor memory device reading/writing data of multiple bits internally
US5369619A · kind A · utility
34Cited by
3References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1991 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | Oct 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array divided into a plurality of block. In one region on the memory chip, four blocks, two input/output circuits, and two data buses are arranged. In the other region on the chip, four blocks, two input/output circuits, and two data buses are arranged. Each block in each region is divided into two sub-blocks corresponding to the two input/output circuits. Each data bus is connected between the corresponding input/output circuit in the same region and the corresponding two sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.