Method of maximizing data pin usage utilizing post-buffer feedback
US5369772A · kind A · utility
4Cited by
13References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 1992 |
| Grant date | Nov 29, 1994 |
| Priority date | — |
| Expiry date | May 21, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved programmable logic device programmed to maximize pin usage, and a method of using such a programmable logic device. The programmable logic device is programmed to use a data pin as an input pin by disabling the output buffer driving that pin. Then, when it is desired to drive the data pin as an output pin, the output buffer is enabled, and the pin is driven by a signal generated by the combinatorial logic on the programmable logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.