Process and arrangement for the Boolean realization of adaline-type neural networks
US5371413A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Mar 4, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A process is stated with which ADALINE-type neural networks whose inputs are Boolean variables can be realized using Boolean functions. In addition, a purely digital circuit arrangement for realizing ADALINE-type neural networks is stated. The digital circuit arrangement can be constructed with the aid of a digital base circuit. The digital base circuit generates the set of Boolean functions which replaces a neuron for any value of its input weighting factors. A process for training the circuit arrangement is stated. It is thus possible to realize and to train ADALINE-type neural networks entirely with the aid of purely digital circuit arrangements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.