Two stage gate drive circuit for a FET
US5371415A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Jun 21, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/04123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A two stage gate drive circuit (10) for controlling a power transistor (12) has been provided. The drive circuit includes a first stage (14) coupled to a first supply voltage terminal for providing a high current drive signal to the power transistor for quickly switching on the power transistor. However, once the power transistor is turned on, the first stage becomes inactive and a second stage (16) coupled to a second supply voltage terminal provides a low current drive signal to the power transistor for fully enhancing the power transistor and lowering its on resistance. The gate drive circuit further includes a timer circuit (18) for rendering the first stage active for predetermined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.