Circuit and method of synchronizing clock signals
US5371416A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Apr 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital clock circuit generates a high-speed clock and window pulses substantially centered about transitions of the high-speed clock in one quadrant of an integrated circuit (IC) and routes the high-speed clock and window pulses to other quadrants of the IC where a low-speed clock generator develops a low-speed clock signal from the window pulses. A control circuit checks alignment between the high-speed and low-speed clock signals and adjusts first and second shift registers to control the delay in generating the low-speed clock as necessary to maintain alignment. The first shift register controls the falling edge of the low-speed clock signal and the second shift register controls the rising edge of the low-speed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.