Digital damping method and apparatus for phase-locked loops
US5371425A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Sep 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the digital damping circuit is a digital circuit which generates adequate phase and frequency damping without a damping resistor. In this manner damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.