Clock extraction and data regeneration logic for multiple speed data communications systems
US5371766A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1992 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Nov 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/422
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Clock extraction and data regeneration logic is provided for a multiple rate digital data communications system such as a local area network (LAN). The logic is implemented in adapters which connect stations in the LAN to other stations in the LAN via transmission media such as wire or fiber optic cable. The clock extraction and data regeneration logic is adapted to quickly recognize the speed at which the token ring is operating, thereby preventing a station on the ring from sending data onto the ring at a rate which does not match the operating frequency of the ring. The logic also performs, at multiple speeds of operation, clock extraction and data reconstruction of a signal received from another station in the ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.