Fuzzy logic controller having high processing speed

US5371832A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Herbert Eichfeld · Munich, DE
• Thomas Kuenemund · Munich, DE

Key dates

• Filing date: Feb 25, 1993
• Grant date: Dec 6, 1994
• Expiry date: Feb 25, 2013

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S706/90
• WIPO field: Control
• WIPO sector: Instruments

Abstract

A fuzzy logic controller is composed of a fuzzification circuit (FUZ), a rule decoder (RDEC), a rule evaluation circuit (RA), an inference circuit (INF), a defuzzification circuit (DFUZ) and a sequencer (CTRL). Numbers (NA) for linguistic values of the output variables together with selection signals (SM) for the definition of the input variables affected by the respective rule formed in the rule decoder and are supplied to the rule evaluation circuit in addition to the values (ME) of the affiliation functions for the linguistic values of the input variables. A weighting signal (G) is generated in the rule evaluation circuit for every linguistic value of the output variables. The advantages obtainable are the high processing speed, the low requirement for chip area, the variable rule format and the selection possibility of different operation modes in the rule evaluation circuit, the inference circuit and the defuzzification circuit.