High speed processor bus extension
US5371863A · kind A · utility
8Cited by
24References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Sep 22, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed, synchronous, processor bus is physically and electrically extended by a bus extension unit to provide data communication between a number of data handling units. The bus extension unit intercouples a system bus to an extended buses for communicating information therebetween. The extension monitors both bus and, upon recognition of an initiation for an information transfer transaction from one bus to the other, will relay the initiation of the transaction, implement the transaction, then relay back any handshake signals that form a part of the transaction, all with a minimum delay of one bus cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.