Method and apparatus for controlling operation of a cache memory during an interrupt
US5371872A · kind A · utility
25Cited by
29References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1991 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Oct 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.