Write-read/write-pass memory subsystem cycle
US5371874A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1993 |
| Grant date | Dec 6, 1994 |
| Priority date | — |
| Expiry date | Aug 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently write the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently write the portion of the transferred data that is most current in the SCU memory and read the written data for transfer to the requesting CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.