Method for forming via hole in multiple metal layers of semiconductor device
US5372971A · kind A · utility
5Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1992 |
| Grant date | Dec 13, 1994 |
| Priority date | — |
| Expiry date | Oct 1, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a via hole in multiple metal layers of the semiconductor device is disclosed. In a via hole forming process of the semiconductor device, a barrier layer is formed beneath the photoresistive layer. Accordingly, the polymer residue formed on the metal-layer pattern and side wall of the via hole is prevented during the plasma etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.