Low-temperature process metal-to-metal antifuse employing silicon link
US5373169A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1992 |
| Grant date | Dec 13, 1994 |
| Priority date | — |
| Expiry date | Dec 17, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.