Planar isolation technique for integrated circuits

US5373180A · kind A · utility

Assignee

• AT&T CORP. · US

Inventors

• Steven J. Hillenius · Summit, US
• William T. Lynch · Apex, US
• Lalita Manchanda · North Plainfield, US
• Mark R. Pinto · Summit, US
• Sheila Vaidya · Watchung, US

Key dates

• Filing date: Sep 14, 1993
• Grant date: Dec 13, 1994
• Expiry date: Sep 14, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/763
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.