Decoder and latching circuit with differential outputs
US5373203A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1993 |
| Grant date | Dec 13, 1994 |
| Priority date | — |
| Expiry date | Apr 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A configurable decode circuit (11) having a plurality of inputs (12), a clock input (13), an output (14), and an output (16) is described. The configurable decode circuit (11) is a nor type decoder configurable to different address widths. A latch (17) stores the decode results. A bias circuit (29) enables the configurable decode circuit (11) starting a decode cycle. A differential input stage is coupled between the latch (17) and bias circuit (29). One side of the differential input stage comprises a plurality of transistors (23) coupled in parallel. Each control electrode of the plurality of transistors (23) is coupled to a respective input of inputs (12). The other side of the differential input stage comprises a transistor (28) coupled between the latch (17) and the bias circuit (29). A control electrode of the transistor (28) is coupled to common first electrodes of the plurality of transistors (23).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.