Chrominance signal processing circuit for a chroma-signal noise reducer
US5373326A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1993 |
| Grant date | Dec 13, 1994 |
| Priority date | — |
| Expiry date | Mar 30, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/83
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A signal from an input terminal (1) is supplied to a video signal processing circuit (2) which derives a carrier chrominance signal. The carrier chrominance signal is supplied through a low-pass filter (3) to an A/D converter circuit (4). A signal converted by the A/D converter circuit (4) is supplied to a bandpass filter (5) which limits the band of the chrominance signal. A signal from the bandpass filter (5) is supplied to a decoder circuit (6) which alternately derives color difference signals (R-Y) and (B-Y). The signal from the decoder circuit (6) is supplied to a decimation filter (7) which effects a decimation. The signal thus decimated is supplied to a multiplexer (8) and thereby generated as 2-bit series data. A signal from the multiplexer (8) is supplied to a CNR (chroma noise reducer) circuit (9). Thus, the number of bits can be reduced without reducing the number of lines of a chroma signal and data gradation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.