Method and apparatus for digitally compensating digital clock skew for high speed digital circuits
US5373535A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1993 |
| Grant date | Dec 13, 1994 |
| Priority date | — |
| Expiry date | Mar 31, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital clock reconstruction circuit comprising a first flip flop, a programmable delay chain, and a first assembly of gates is provided to digitally compensate an entering digital clock's skew for a high speed digital circuit by digitally reconstructing the entering clock. The reconstructed clock will also provide the minimum amount of high and low time in a period required by the components of the high speed circuit. Additionally, at least one measurement or comparison circuit is provided for measuring the frequencies of the reconstructed clock under various delay settings of the programmable delay chain to calibrate the digital clock reconstruction circuit. Under the calibration process of the present invention, the delay setting is determined iteratively, starting from an initial setting and varying the delay setting in a predetermined manner. In the preferred embodiment, a ring oscillator is also provided to guide the selection of the starting delay setting, and multiple measurement and comparison circuits are provided. The measurement and comparison circuits are used to collect various measurements to monitor the digital clock reconstruction circuit during normal operation …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.