Semiconductor memory device

US5374839A · kind A · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Jun-Young Jeon · Seoul, KR
• Hoon Choi · Seoul, KR
• Dong-Il Seo · Daejeon, KR

Key dates

• Filing date: Mar 30, 1993
• Grant date: Dec 20, 1994
• Expiry date: Mar 30, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/50

Abstract

A semiconductor memory device, e.g., a DRAM, which includes a P-type semiconductor substrate, a memory array each memory cell of which includes at least one N-channel MOS transistor, a CMOS peripheral circuit at least partially surrounding the memory array, the peripheral circuit including at least one P-channel MOS transistor formed in an N-type well region formed in the substrate, and at least one N-channel MOS transistor formed in the substrate outside of the N-type well region, and, a P-type minority carrier absorption semiconductor region formed in the substrate between the N-type well region and the memory array. The minority carrier absorption semiconductor region is preferably connected to a source of negative voltage, e.g., the substrate bias voltage, and a separate N-type region formed in the N-type well region is preferably connected to a source of positive voltage, e.g., the power supply voltage, Vdd, of the memory device. The N-type well region functions to absorb or capture hot electrons generated by the N-channel MOS transistor of the CMOS peripheral circuit, and the P-type minority carrier absorption semiconductor region functions to absorb or capture holes which wo…