Multi-tap digital delay line
US5374860A · kind A · utility
40Cited by
4References
59Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 15, 1993 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Jan 15, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable digital delay line having N delay elements, two multiplexers connected to the output of the delay elements, and a comparator connected to the outputs of the multiplexers is disclosed. The invention teaches an apparatus and a method of delaying a signal, while reducing the number of delay elements and the number of connections to multiplexers. In a first embodiment of the invention, the delay elements are inverters or differential delay elements. In a second embodiment, the delay elements are differential delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.