Wiring routes in a plurality of wiring layers
US5375069A · kind A · utility
149Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1994 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Jan 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wiring processing method for determining a wiring route for connecting terminals includes a step of dividing a wirable region into a plurality of rectangular regions in a virtual region corresponding to a chip, a step of searching a rectangular region for connecting the terminals to be wired by tracing mutually crossings rectangular regions, and a step of determining a detailed wiring route inside the searched rectangular region. Since the search is conducted by use of the rectangular region as a unit, high speed search can be made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.