Three-dimensional ferroelectric integrated circuit without insulation layer between memory layers
US5375085A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1992 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Sep 30, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/00
Abstract
A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.