First-in first-out memory device
US5375092A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1993 |
| Grant date | Dec 20, 1994 |
| Priority date | — |
| Expiry date | Jun 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to enable enlargement/reduction of data with a simple structure in a first-in first-out memory device thereby reducing the circuit scale of this device, output terminals (Q.sub.0 to Q.sub.3) of a read clock counter (16) are shifted to low order digits and connected to input terminals (A.sub.0 to A.sub.2) of a read address decoder (18). The read clock counter (16) and a read data sense amplifier (19) operate in response to read clocks (RK2). Enlarged read data (RD) are outputted from the read data sense amplifier (19). It is possible to implement enlargement/reduction of data by changing connection between the read clock counter (16) and the read address decoder (18), thereby remarkably simplifying the circuit structure of the first-in first-out memory device having an enlargement/reduction function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.